1. Field of the Invention
The present invention relates to a device for controlling the writing of branch history information in an information processing apparatus provided with a branch estimation unit.
2. Description of the Related Art
In an instruction execution processing apparatus, performance is improved by using technologies including a pipeline process and sequentially starting the execution of subsequent instructions without waiting for the completion of a specific instruction. In this case, if a previous instruction is an instruction to change the execution sequence of a subsequent execution, such as a branch instruction, etc., and a branch is established, the execution pipeline is impeded, and in the worst case, the performance is degraded if an instruction on the branch destination is not inputted to the execution pipeline. Under these circumstances, a branch prediction unit represented by a branch history is provided and the establishment of a branch is predicted. If a branch establishment is predicted, the performance could be improved by inputting an instruction on the branch destination following a branch instruction to an execution control unit or instruction process unit.
However, in a conventional branch prediction unit, the branch history information of a branch instruction of which the execution is completed in a branch control unit was registered in a branch history by temporarily stopping the instruction fetch.
According to this system, in particular, if a branch prediction fails and a correct subsequent instruction is re-executed, and specifically, if a re-instruction fetch occurs, an instruction fetch pipeline is temporarily stopped by the branch history information writing the completed branch instruction into the branch history although the frequency of a fetch request is high since a temporary instruction buffer is empty. Accordingly, the performance was not improved.
Specifically, although, as in the execution of a branch instruction BC shown in FIG. 1, in the cycle W of the execution cycle of a branch instruction, the branch history information is written into the branch history, only one access can be allowed at one time since the branch history is comprised of RAMs (random access memory). Accordingly, the re-instruction fetch of the branch destination instruction is started one clock cycle behind the cycle W of the branch instruction.
The branch history information is to be written in the branch history when it can be completed in the branch control unit, and is not written at the time of actual branch execution completion. Accordingly, if an interruption occurs immediately before the branch execution, a return address stack is sometimes operated by mistake.
If there is a short loop, especially in an instruction string as shown in FIG. 2A, this instruction string can be fetched at one instruction fetch. Therefore, the timing becomes as shown in FIG. 2B, and the branch history information is written later than the re-instruction fetch. If there is a branch instruction to be looped immediately after the re-instruction fetch, etc., a correct branch cannot be predicted. In this case, since one more re-instruction fetch is executed, the performance is degraded.